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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
FEATURES
* 16-bit transparent latch * Multiple VCC and GND pins minimize
switching noise
DESCRIPTION
The MB2373 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The MB2373 device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates. The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present
one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation. When nOE is Low, the latched or transparent data appears at the outputs. When nOE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
* Power-up 3-State * Live insertion/extraction permitted * Power-up reset * 3-State output buffers * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per
JEDEC JC40.2 Std 17
* ESD protection exceeds 2000V per MIL
STD 883 Method 3015 and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V TYPICAL 2.9 4 7 500 UNIT ns pF pF nA
ORDERING INFORMATION
PACKAGES 52-pin plastic Quad Flat Pack TEMPERATURE RANGE -40C to +85C ORDER CODE MB2373BB DRAWING NUMBER 1418B
PIN CONFIGURATION
GND GND GND 1OE 1Q3 1Q2 1Q1 1Q0 1D0 1D1 1D2 1D3 1E
LOGIC SYMBOL
52 51 VCC 1Q4 1Q5 GND 1 2 3 4 5 6 7 8 9
50 49 48 47
46 45 44 43 42
41 40 39 V CC 38 1D4 37 1D5 36 GND 35 1D6 48 49 51 52 2 1Q0 1OE 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1E 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 44 43 41 40 38 37 35 34 8 9 11 12 14 15 17 18 2Q0 2OE 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2E 2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 32 31 29 28 26 25 23 22
47 45
19 21
1Q6
1Q7 GND
MB2373 52-pin PQFP
34 1D7 33 GND 32 2D0 31 2D1 30 GND 29 2D2 28 2D3 27 V CC
2Q0
2Q1
GND 10 2Q2 11 2Q3 12 VCC 13 14 15 16 2Q4 2Q5 GND 17 18 19 20 2Q6 2Q7 2OE GND 21 22 23 24 25 2E GND 2D7 2D6 2D5 26 2D4
August 23, 1993
E E E
E E E
3 5 6
1
853-1669 10587
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
PIN DESCRIPTION
PIN NUMBER 44, 43, 41, 40,38, 37, 35, 34, 32, 31, 29, 28, 26, 25, 23, 22 48, 49, 51, 52, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18 47, 19 45, 21 4, 7, 10, 16, 20, 24, 30, 33, 36, 42, 46, 50 1, 13, 27, 39 SYMBOL 1D0 - 1D7 2D0 - 2D7 1Q0 - 1Q7 2Q0 - 2Q7 1OE, 2OE 1E, 2E GND VCC Data inputs Data outputs Output enable inputs (active-Low) Enable inputs (active-High) Ground (0V) Positive supply voltage FUNCTION
LOGIC SYMBOL (IEEE/IEC)
47 45 C1 EN 19 21 C1 EN
44 43 41 40 38 37 35 34
1D
48 49 51 52 2 3 5 6
32 31 29 28 26 25 23 22
1D
8 9 11 12 14 15 17 18
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nE
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
FUNCTION TABLE
INPUTS nOE L L L L L nE H H L nDx L H i h X INTERNAL REGISTER L H L H NC OUTPUTS nQ0 - nQ7 L H L H NC Enable and read register Latch and read register Hold Disable outputs OPERATING MODE
H= h= L= l= NC= X= Z= =
H L X NC Z H H Dn Dn Z High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 10 +85 LIMITS MAX 5.5 VCC V V V V mA mA ns/V C UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II IOFF IPU/PD IOZH IOZL IO ICEX ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output voltage3 Input leakage current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output current1 Output High leakage current VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = GND VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 2.5V VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 TYP -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 -70 5.0 120 44 120 0.5 0.55 0.55 1.0 100 50 50 -50 -180 50 250 60 250 1.5 -50 MAX -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 -180 50 250 60 250 1.5 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A A A A A mA A A mA A mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transition time of up to 100sec is permitted.
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay nDx to nQx Propagation delay nE to nQx Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 1.3 1.3 1.8 2.0 1.2 2.1 1.4 2.0 Tamb = +25oC VCC = +5.0V TYP 2.8 2.9 3.5 3.5 2.9 3.8 3.7 3.6 MAX 4.1 4.1 4.9 4.9 4.1 5.3 5.0 4.6 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.3 1.3 1.8 2.0 1.2 2.1 1.4 2.0 MAX 4.8 4.8 5.7 5.5 5.1 6.1 5.5 5.1 ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low nDx to nE Hold time, High or Low nDx to nE Enable pulse width High 3 3 1 1.0 1.0 0.5 0.5 2.5 +25oC TYP 0.0 0.3 -0.2 0.0 1.0 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.0 1.0 0.5 0.5 2.5 ns ns ns UNIT
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
AC WAVEFORMS
nE
VM
VM
VM
nDx
VM
VM
tw(H) tPHL
tPLH tPLH
tPHL
nQx
nQx
VM VM
VM
VM
Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width
nDx
VM
ts(H)
nE
Waveform 3. Data Setup and Hold Times
nOE
VM tPZH
VM tPHZ VOH -0.3V
nQx
VM
0V
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
NOTE: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
August 23, 1993
EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E
VM VM VM th(H) ts(L) th(L) VM VM
EEE EEE EEE EEE EEE
Waveform 2. Propagation Delay for Data to Outputs
nOE
VM tPZL
VM tPLZ
nQx
VM
VOL +0.3V 0V
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
6
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T CL RL VOUT RL
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
AMP (V)
0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V)
Test Circuit for 3-State Outputs
POSITIVE PULSE 10%
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude MB 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
6 5
tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx
4 3 MAX 2 4.5VCC 5.5VCC Offset in ns 1 0 MIN -1 -2
Adjustment of tPLH for Load Capacitance and # of Outputs Switching nDx to nQx
4 ns 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125
16 switching 8 switching 1 switching
0
50
100
150
200
C tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx
pF Adjustment of tPHL for Load Capacitance and # of Outputs Switching nDx to nQx
6 5
4 3 MAX 2 4.5VCC 5.5VCC Offset in ns 1 0 MIN -1 -2
4 ns 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125
16 switching 8 switching 1 switching
0
50
100
150
200
C tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nE to nQx
pF Adjustment of tPLH for Load Capacitance and # of Outputs Switching nE to nQx
4 3 MAX 2 4.5VCC 5.5VCC MIN Offset in ns 1 0 -1 -2
7 6 5 ns 4 3 2 1 -55 -35
16 switching 8 switching 1 switching
-15
5
25
45
65
85
105
125
0
50
100
150
200
C
pF
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
7 6 5 ns 4 3 2 1 -55 -35
tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nE to nQx
4 3 MAX Offset in ns 2 1 0 -1 -2
Adjustment of tPHL for Load Capacitance and # of Outputs Switching nE to nQx
16 switching 8 switching 1 switching
4.5VCC 5.5VCC MIN
-15
5
25
45
65
85
105
125
0
50
100
150
200
C tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx
6 5 4
5 4 MAX 3 4.5VCC Offset in ns 2 1 0 MIN
16 switching 8 switching 1 switching
ns
3 5.5VCC 2 1 0 -55 -35 -15 5 25 45 65 85 105 125
-1 -2 0 50 100 150 200
C tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx
7 6 5
4 3 2 4.5VCC Offset in ns 1 0 -1 -2
MAX
16 switching 8 switching 1 switching
ns
4 3 2 1 -55 -35 -15 5 25 45 65 85 105
5.5VCC
MIN
125
0
50
100
150
200
C
pF
August 23, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
7 6 5 4 ns 3 2
tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
5 4 MAX Offset in ns 3 2 1 0 MIN -1 -2
Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx
16 switching 8 switching 1 switching
4.5VCC 5.5VCC
1 0 -55 -35 -15 5 25 45 65 85 105 125
0
50
100
150
200
C tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx
6
6 5
5
MAX Offset in ns
4 3 2 1 0 -1
16 switching 8 switching 1 switching
4 ns
4.5VCC 5.5VCC
3 MIN
2
1 -55 -35 -15 5 25 45 65 85 105 125
-2 0 50 100 150 200
C tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching
9 7 4 5 ns 3 4.5VCC 5.5VCC Offset in ns 3 1 -1 1 -55 -35 -15 5 25 45 65 85 105 125 -3 0 50
pF
Adjustment of tTLH for Load Capacitance and # of Outputs Switching
5
16 switching 8 switching 1 switching
2
100
150
200
C
pF
August 23, 1993
10
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual octal transparent latch (3-State)
MB2373
4
tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching
Adjustment of tTHL for Load Capacitance and # of Outputs Switching
4 3 16 switching 8 switching 1 switching
3 2 ns 2 4.5VCC 5.5VCC Offset in ns 1 0 -1 0 -55 -35 -15 5 25 45 65 85 105 125 -2 0 50 100 150
1
200
C
pF
4.0 3.5 3.0 2.5 Volts
VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V
125C 25C -55C
5 4 3 2 1 0
VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V
125C 25C -55C
1.5 1.0 0.5 0.0 125C 25C -55C 0 50 100 150 200
Volts
2.0
125C 25C -55C
-1 -2 0 50 100 150 200
-0.5
pF
pF
August 23, 1993
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